Author(s): Rajesha N, Pushpavathi G

Email(s): rajeshmurthy44@gmail.com

DOI: 10.5958/2321-581X.2019.00007.2   

Address: Rajesha N1, Pushpavathi G1
1Dept. of ECE, Malla Reddy Institute of Engineering and Technology, Secunderabad, India.
2Dept. of Physics, Malla Reddy Institute of Engineering and Technology, Secunderabad, India
*Corresponding Author

Published In:   Volume - 10,      Issue - 1,     Year - 2019


ABSTRACT:
Field programmable Gate Arrays (FPGAs) are broadly used to actualize special purpose processors. FPGAs are financially savvy for little parcel creation since functions and interconnections of rationale assets can be straightforwardly modified by end users. In spite of their outline cost advantage, FPGAs force expansive dynamic and standby power utilization overheads contrasted with custom silicon options. This work shows a field-programmable Gate Array (FPGA) in light of look up table level fine-grain power gating with little overheads. The power gating strategy executed in the proposed architecture can straightforwardly recognize the movement of every turn upward table effortlessly by abusing elements of asynchronous architectures. In addition, identifying the information entry ahead of time keeps the postpone increment for awakening and the power utilization of pointless power exchanging. Since the power gating system has little overheads, the granularity size of a power-gated space is as fine as a single two-input and one-output lookup table. Contrasted with a LEDR (Level-Encoded Dual-Rail) based FPGA, the FPGA situated in light of the proposed fine grain power gating system consumes power is 42% less.


Cite this article:
Rajesha N, Pushpavathi G. Design of a Reconfigurable Stumpy FPGA In view of Fine-Grain Power Gating. Research J. Engineering and Tech. 2019;10(1):33-39. doi: 10.5958/2321-581X.2019.00007.2


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DOI: 10.5958/2321-581X 


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