Multicore processor is a single processor which contains number of cores on a chip. The cores are functional units made up of computation units and caches. In multicore System cache allocation technology helps address shared resource concerns by providing software control of where data is allocated into the cache, enabling isolation and prioritization of key applications. In this paper, cache replacement policies and cache allocation technology are discussed. A cache allocation technology keeps performance up of processor and protects form timing attacks where replacement policies determine which data blocks should be removed from the cache when a new data block is added. We also analyses the performance of L1 instruction and Data caches with different replacement policies such as LRU (Least Recently Used), FIFO (First In First Out), RANDOM, PLRU (Pseudo Least Recently Used) on the performance of L1 instruction and Data caches.
Cite this article:
Dhammpal Ramtake, Sanjay Kumar. Cache Replacement and Allocation Technology in Multicore System: A study of Security Issue. Research J. Engineering and Tech. 2020;11(2):103-108. doi: 10.5958/2321-581X.2020.00018.5
1. Alan Jay Smith, “Cache memory”, Computing Surveys, ACM 0010-4892/82/0900-0473, Vol. 14, No. 3, September 1982, pp 473-531.
2. Introduction to Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family, https://software.intel.com/content/www/us/en/develop/articles/introduction-to-cache-allocation-technology.html retrieved as on dated 10-01-2020.
3. M. D. Hill and A. J. Smith, “Evaluating associativity in CPU caches”, IEEE Transactions on Computers, Vol. 38, No. 12, December 1989, pp 1612-1630.
4. Improving Performance by Utilizing Cache Allocation” Intel’s White Paper, Document number 331843-001US, 2015, pp 2- 15.
5. Dhammpal Ramtake and Sanjay Kumar, ”Performance Analysis of First Level Cache memory Replacement Policies in Multicore Systems”, IJERCSE, vol. 5, pp 505-511, 2018.
6. A.Malamy, R.Patel and N.Hayes, “Methods and Apparatus for Implementing A Pseudo-LRU Cache Memory Replacement Scheme with A Locking Feature”, United States Patent, patent no. 5353425, October 1994.
7. Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr. , Joel Emer, “Adaptive Insertion Policies for High Performance Caching”, Proceedings of the 34th annual international symposium on Computer architecture (ISCA’07), ACM, ISBN: 978-1-59593-706-3, June 2007, pp 381-391.
8. John P.Hayes, “Computer Architecture and organization”, Third Edition Tata McGraw Hill, ISBN: 0-7-0027355-3, 1998, pp 451-452.
9. Anastasiia Butko, Rafael Garibotti, Luciano Ost and Gilles Sassatelli, “Accuracy Evaluation of GEM5 Simulator System”, 2012
10. Abu Asaduzzaman, Fadi N. Sibai, Manira Rani “Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level”, Journal of Systems Architecture 56, Elsevier, 2010, pp 151–162.
11. Hussein Al-Zoubi, AleksandarMlienkovic, Milena Mlienkovic,”Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suit”, ACMSE’04, ACM, ISBN: 1-58113-870-9, Apr 2004, pp 267-272.
12. Vinh Ngo Quang and Hao Do ”Exploring Cache Coherency Design for Chip Multiprocessor using Multi2Sim”, International Journal of Engineering Research & Technology (IJERT) ,vol. 4, PP. 775-779, 2.