V. Rama Raju, Y. Sri Lakshmi, E. Brahma Reddy
V. Rama Raju1, Y. Sri Lakshmi2, E. Brahma Reddy3
1Principal & Professor, ECE & CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP
2Asst. Professor, ECE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP
3Associate Professor, CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP
Volume - 3,
Issue - 4,
Year - 2012
Leakage (or static power consumption) and Glitches are two of the major problems faced by the semiconductor nanometer technologies. This project develops new power minimization methods for digital CMOS circuits considering two components of power, namely, the leakage power and the glitch power are minimized while the overall circuit delay is controlled. Arithmetic circuits like adders and multipliers are essential components in the design of circuits in ASIC. To design low power high sped arithmetic circuits a combination of techniques at four levels is required. They are Algorithm, architecture, circuit and system levels. With the continuous increase of the density and performance of integrated circuits due to the scaling down of the CMOS technology, reducing power dissipation becomes a serious problem that every circuit designer has to face. Digital multiplication is not the most fundamentally complex operation, but is the most extensively used operation. Innumerable schemes have been proposed for realization of the operation. Various multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the TG-multiplier dissipates less energy than other traditional array multipliers. By combining transmission gates with static CMOS in TG-multiplier architecture, a new approach is proposed to improve the energy-efficiency for low-power architectures. The project consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of Vdd-to-ground paths also contributes to a significant decrease of static consumption.
Cite this article:
V. Rama Raju, Y. Sri Lakshmi, E. Brahma Reddy. Computerized Model Development of Glitch Reduction in Low-Power Low-Frequency TG- Multiplier. Research J. Engineering and Tech. 3(4): Oct-Dec. 2012 page 262-269.
V. Rama Raju, Y. Sri Lakshmi, E. Brahma Reddy. Computerized Model Development of Glitch Reduction in Low-Power Low-Frequency TG- Multiplier. Research J. Engineering and Tech. 3(4): Oct-Dec. 2012 page 262-269. Available on: https://ijersonline.org/AbstractView.aspx?PID=2012-3-4-3